We show how design-for-yield (DFY) and design-for-manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced to 90 nm and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect-limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g., IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conduct their own research in the area, and to apply these concepts in their jobs.

The objective of this course is to present existing industrial techniques to meet the ever-increasing test complexity challenges of analog and high-speed IO’s. We will present ATE and new innovative solutions to test mixed-signal and RF SOCs. These new techniques greatly rely upon DFT and BIST structures. The tutorial presents the basic concepts in analog and RF measurements (eye diagram, jitter, gain, power compression, harmonics, noise figure, phase noise, BER, EVM, etc.). Several industrial examples of production testing of mixed-signal and RF devices, such as, SERDES transceivers, PHYs, HSIO, and RF transceivers are also presented. The block-DFT solutions are presented for PLLs, squelch detectors, equalizers, CDR, mixers, AGC, LNAs, DACs and ADCs. The testing of high-speed IO interfaces, such as, PCI-Express, and XAUI, etc, and the new design trends in RF systems such as MIMO, LTE, NFC and SIP based systems and their testability are also presented in this tutorial.

The gap between working silicon and a working board/system is becoming more significant and problematic as technology scales and complexity grows. The result of this increasing gap is failures at the board and system level that cannot be duplicated at the component level. These failures are most often referred to as “NTFs” (no trouble founds). The result of these NTFs can range from higher manufacturing costs and inventories to failure to get the product out of the door. The problem will only get worse as technology scales and will be compounded as new packaging techniques (SIP, SOC, 3D) extend and expand Moore’s law. This is a problem that must be solved, yet, little effort has been applied up to this point. This tutorial will provide a detailed background on the nature of this problem and will provide DFT and test solutions at both the component and board/system level.

Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This tutorial provides knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during test application. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low-power design techniques and shows how these low power devices can be tested safely without affecting yield and reliability. EDA solutions for considering power during test and design-for-test are also discussed in the last part of the tutorial.

The objective is to provide attendees with an overview of fault modeling, test design, BIST and BISR for memory devices in the nano-era. Traditional fault modeling and recent development in fault models for current and future technologies are covered. Systematic methods are presented for designing and optimizing tests, supported by industrial results from different companies (e.g., Intel, ST, Infineon) and for different technology nodes (e.g., 0.13 um, 65 nm). Impact of algorithmic (e.g., data-background) and nonalgorithmic (e.g., voltage) stresses is explored in order to get better insight in the test effectiveness. State-of-the art and novel BIST architectures are covered; special attention is given to the optimization of address generator designs as they typically consume considerable BIST area overhead. BISR and redundancy analysis are also discussed. Moreover, CPU-based memory test―which is in some applications the only resource to perform at least the power-on tests―is addressed. Finally, future challenges in memory testing are highlighted.

Test economics provides a way of quantifying the costs and benefits of test, and helps a test engineer choose an effective test strategy. Classical microeconomics is far more sophisticated than what is found in test economics papers. Recent work in behavioral economics, known to the public through bestsellers such as “Freakonomics” and "Predictably Irrational," has shown that classical assumptions about the behavior of economic actors are wrong. This tutorial will summarize existing work in test economics, provide background on microeconomic and behavioral economics concepts that are of interest to test and DFT engineers, and will show their applicability to test. The student will emerge with the ability to do traditional cost and benefit modeling, and with a deeper understanding of the economic principles that affect the cost and benefits of test. The researcher will emerge with the tools to make a much better case for the benefits of proposed research.

We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing, such as reducing costs that are increasingly dominated by MS functions. Next, we discuss trends in standardized DFT, including IEEE 1149.1, .4, .6, .8, and 1687. The trend analysis concludes with a review of DFT/BIST techniques, including fault simulation. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, random analog, and briefly RF. Next, seven essential principles of practical analog BIST are presented in detail. Lastly, we discuss the most-practical DFT and BIST techniques, ranging from the classic analog bus, to mostly-digital oversampling and undersampling methods that greatly improve range, resolution, and reusability. Examples and case studies are included. Attendees will gain a clear picture of where they are keeping up with industry, the roadblocks to analog BIST adoption, and how to make parametric DFT/BIST, diagnosis, and testing more systematic.

This is an advanced tutorial covering fundamental concepts, research ideas and industry practices on validating and testing integrated circuits for speed failures. The intended audience is a combination of semiconductor industry practitioners, EDA technologists, and researchers in digital test. The tutorial starts with a discussion of defects and design marginalities that induce a circuit to fail at its rated speed while passing at a lower speed. This is followed by fault models and fault sensitization conditions, covering classical models such as transition faults and path delay faults, and models that capture crosstalk, voltage droop, multiple-input switching and charge-sharing. It then discusses test generation, fault simulation and diagnosis algorithms. design-for-test techniques that facilitate application of delay tests, metrics to measure test quality, and techniques to improve test quality and reduce yield loss are then discussed. Finally, applications in post-silicon validation, speed binning and in-field reliability are discussed using industry case studies.

Integrated circuits have traditionally all been tested identically in the manufacturing flow with little sharing of test results between the different test insertions. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by subjecting “suspect” parts to more extensive testing, and also adaptively bring in additional tests that target the suspected failure mode. The idea is analogous to selective security screening approaches applied at airports. Such statistical methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on production digital and analog circuits from IBM, Intel and LSI, Analog Devices and NXP Semiconductor. Commercial tools offered by a number of new companies that have emerged in the "adaptive test" space will also be discussed. Broadly, these aim provide to support for the sharing and leveraging of results from the different tests in the test flow for effective test adaptation and optimization.

Modern chips have a wealth of embedded content and are becoming more complex in architecture with SOCs being made up of multiple cores and with multiple-TAP configurations; and known-good-die being stacked into SIPs, POPs, and 3-D SICs. The need for access to embedded instruments for debug, validation, test and yield analysis on various occasions during a chip’s life-cycle are driving the industry toward “standard” solutions instead of collections of ad hoc access mechanisms. These solutions include IEEE 1149.1, 1500, 1149.7 and P1687, which provide for, respectively, the original standard test access port (TAP), embedded core test, the reduced-pin and enhanced-functionality TAP, and access and control of instrumentation. This tutorial will familiarize the student with IEEE 1500 and P1687, particularly, will present the drivers for adoption and use of the standards, will show examples of architectures and usage, and will evaluate pros and cons associated with implementation and use.

Three-dimensional stacked ICs offer dense integration of possibly heterogeneous technologies at a small footprint. Interconnection of the various tiers by means of through-silicon Vias (TSVs) promises to increase the interconnect bandwidth and performance while lowering power and manufacturing cost, and hence might help the semiconductor industry to extend the momentum of Moore’s Law into the next decade. Testing for manufacturing defects is considered by many as a major, still largely unresolved obstacle to make 3-D integrated circuits a reality. There are concerns about the cost, or even worse, feasibility of testing such TSV-based 3-D chips. In this tutorial, we present the challenges and solutions for a practical 3-D test approach. We discuss the various test flows in 3D-SIC testing based on known-good-die (KGD) and known-good-stack (KGS) testing, and the role of modular testing. We present the new defects and tests for intra-die defects (e.g., due to wafer thinning) and TSV-based interconnects, and the wafer test access challenges related to KGD and KGS testing. We present recent advances in pre-bond testing that targets dies and TSVs. Finally, we discuss an on-chip design-for-test (DFT) architecture that supports a modular test approach for 3-D ICs.

This is a relatively broad tutorial covering how a IC designer’s decisions and IDM technology node requirements can dramatically affect device testing practices and the associated infrastructure requirements (i.e., probe cards, tester hardware, and metrology systems). Advanced and MEMS probe technologies clearly dominate the memory segment; however, the volumes and demands of advanced probe cards for non-memory applications are growing rapidly. Probe requirements driving these test tooling technologies include device I/O configurations, good/bad die identification, traditional vs. advanced and MEMs probe technologies, temperature effects, and other factors that can affect cost of test. For characterizing and improving wafer sort to meet advanced technology node challenges, the role of advanced probe card metrology tools and closed loop practices for process improvement will be considered. Challenges faced by memory and logic probe testing that include the cost pressures behind multisite and massively parallel wafer sort will be compared and contrasted. High-volume manufacturing (HVM) sort floor challenges and solutions for reduced probe card repairs, online cleaning to maintain high yield and throughput, and I/O damage control will be covered.

Testability is a fundamental requirement for today’s systems-on-chip. These integrated circuits are typically designed based on intellectual property (IP) block integration to make the best use of the millions of gates available. Logic and memory IP blocks require adequate fault detection, silicon debug and yield optimization, all of which are based on testability infrastructure built into the systems-on-chip. This tutorial presents the fundamental knowledge base that any designer or testability engineer must have in order to fulfill the current industrial best practices for design-for-testability. The tutorial discusses the requirements for block-level test architecting, at-speed design practices, scan compression, memory self-test, debug and repair, test interface standardization efforts such as IEEE Std 1149.1 (JTAG) and IEEE Std. 1500, and integration for system-on-chip levels and beyond. Actual industrial experiences will be shared with the audience whenever possible.

Hardware security and trust is an important design objective similar to power, performance, reliability and testability. We will highlight why hardware security and trust are important objectives from the economics, security, and safety perspectives. Important learning outcomes of this tutorial include (i) understanding simple “gotchas” when traditional DFT, test, and validation techniques are used (scan chains, JTAG, SOC test, assertion-based validation), (ii) understand how traditional DFT, test and validation techniques can be used to improve hardware security and trust and finally (iii) understand “design-for-trust” approaches that can provide testability without compromising security and trust.